1. Field of the Invention
The present invention generally relates to a method for manufacturing a metal-oxide-semiconductors transistor, and more particularly to a method that control the extension lateral diffusion by using a double etch spacer.
2. Description of the Prior Art
In the field of metal oxide semiconductors, the length of the channel becomes shorter as the size of the device is decreased, and the operation time will become shorter, too. However, the length of channel of MOSFET cannot be infinitely shortened, because the short channel of device will result in some problems. This problem is the so-called short channel effect.
The hot carrier effect will be more serious as the channel of the MOSFET is further shortened. There are many methods to solve the issue, and one of them is to lower the operation voltage of the MOSFET. If, for example, the voltage is lowered from 5 V to 2.5 V, the electric field will become too weak to result in hot carrier, and hot carrier effect will be lessened effectly. Another method to lessen the hot carrier effect at least includes the lightly doped drain (LDD), and is called as extension while the concentration is increased. In such a way, a low concentration N-type region is added into a portion of the region of the source/drain region of the MOSFET, and the region is near the channel of the device.
In a conventional process, a substrate is provided with the gate oxide layer in the metal oxide semiconductors, and a gate is formed on it, and an extension is formed by implanting numerous first ions in the substrate, and then the spacer is formed on the sidewalls of the gate. Then the source/drain region is formed by implanting numerous second ions in the substrate. Because a gate is formed, an extension is first formed and then the source/drain region is formed, wherein an extension can be effective to avoid many times thermal process and initial lateral diffusion, such as deposition reaction and ion implantation. If the width of the effective channel length is too short, the short channel effect will be more severe.
For the foregoing reasons, there is a need for a method of forming extension by using double etch spacer to solve the short channel effect.
In accordance with the present invention, a method is provided for forming extension by using double etch spacer of MOS and substantially can be used to solve the lateral diffuse issue of the conventional process.
One of the objectives of the present invention is to permit extension to accept less and less of a thermal process.
Another of the objective of the present invention is to control the strength of the short channel effect for suppressing the short channel effect in deep submicron.
A further objective of the present invention is to control the strength of the spacer for collocating lateral diffuse by using a double etch spacer.
In order to achieve the above objects of this invention, the present invention provides a method for forming extension by using double etch spacer. The method at least includes the following steps. First of all, a semiconductor substrate is provided. Then, the gate on the substrate is formed. A first spacer is formed on a sidewall of the gate. Then, numerous first ions are implanted in the substrate by a mask of both the gate and the first spacer to form a source/drain region. Then, the second spacer is formed by etching the first spacer, wherein the width of the second spacer is less than the width of the first spacer. Finally, numerous second ions are implanted in the substrate by a mask of both the gate and the second spacer to form an extension.